Packet processing apparatus for realizing wire-speed, and method thereof

ABSTRACT

Provided are a packet processing apparatus for realizing a wire-speed, and a method thereof. The packet processing apparatus realizes a wire-speed by making an inputted packet be processed in another packet processing apparatus instead of processing the inputted packet for itself. The packet processing apparatus for realizing a wire-speed by having an inputted packet processed in a packet processor of another packet processing apparatus by making an inputted packet detour a packet processor into a detour path, includes: a packet classifier for classifying and storing the inputted packet in a multi-queue based on a priority; a queue manager for including the multi-queue, determining a detour packet among packets stored in the multi-queue and marking the packet as a detour packet; and a packet scheduler for transmitting the packet designated as the detour packet to the detour path. The apparatus is used for a packet communication system.

FIELD OF THE INVENTION

The present invention relates to a packet processing apparatus forrealizing a wire-speed, and a method thereof; and, more particularly, toa packet processing apparatus for performing a packet process by usingnot only resources within the corresponding packet processing apparatus,which used to be used in a conventional technology but also resources ofanother available packet processing apparatus in a packet communicationsystem.

DESCRIPTION OF RELATED ART

A transmitting system and a receiving system of a packet communicationsystem include a plurality of line cards and more than one port isarranged in each line card. Herein, a port of the transmitting systemand a port of the receiving system are connected and the transmittingsystem transmits a packet to a receiving port of the receiving system ata predetermined maximum speed through a transmitting port whenever apacket to be transmitted is generated. The speed is called a wire-speed,which is a physically possible maximum transmission speed of a link. Forexample, 2.5 Gbps in Packet over SONET (POS) OC48 communication port and1 Gbps in a gigabit Ethernet communication port correspond to thewire-speed.

When the receiving system can receive and process all packetstransmitted from the transmitting system at the maximum speed, it isapproved that the packet communication system has a process performanceof a wire-speed with respect to the packet. Although the receivingsystem should process all packet transmitted to the wire-speed, there isa case that some packets cannot be processed. This is because the linecard of the receiving system may not process all packets can begenerated.

To have a look at the process of the receiving system, the packetentering through the receiving port stays for a while in a queue beforethe process. When the first entering packet is processed in a packetprocessing block in the inside of the line card, the packet staying inthe queue is transmitted to the packet processing block in sequence andprocessed. Therefore, when a speed for filling the packet in the queueis slower than a speed for processing the packet in the packetprocessing block, the queue is gradually filled with the packet and thepackets entering the queue after the queue is filled with the packet aredestroyed since there is no room for the packets to be kept. That is,there is a problem that a case that the packet is not processed in thewire-speed.

Also, the line card can receive diverse packets, and a process andrequired time of the received packet are different from each other.Generally, it takes a long time to process a complicated packet and acomparatively short time to process a simple packet. When the line cardis designed, the process performance of the line card is determined inconsideration of probability distribution. Herein, when a high-speedprocessor is selected, a possibility to process the packet without anyloss is raised. However, selecting the high-performance processor toreduce the packet loss has a problem that the cost is high.

Also, much of the packet process is performed by making use of hardware.However, some packet process functions can be processed by usingsoftware since processing all parts of an option header of the packet bythe hardware method does not bring any profit by making a hardware logiccomplicate and raising a cost. Accordingly, delay can be caused in aprocess of a specific packet. When the delay occurs frequently, thedelays of the packet process are accumulated and the queue is filledwith the packets, and eventually this causes the packet loss.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a packetprocessing apparatus for realizing a wire-speed by making an inputtedpacket be processed in another packet processing apparatus instead ofprocessing the inputted packet, and a method thereof.

It is another object of the present invention to provide a packetprocessing apparatus for realizing wire-speed of the packetcommunication system by processing both packets, which are processed inthe other packet processing apparatus and transmitted, and packets,which are not processed in the other packet processing apparatus andtransmitted.

Other objects and advantages of the invention will be understood by thefollowing description and become more apparent from the embodiments inaccordance with the present invention, which are set forth hereinafter.It will be also apparent that objects and advantages of the inventioncan be embodied easily by the means defined in claims and combinationsthereof.

In accordance with an aspect of the present invention, there is provideda packet processing apparatus for realizing a wire-speed by making aninputted packet detour a packet processor into a detour path andprocessing the inputted packet in a packet processing means of anotherpacket processing apparatus, which is a second packet processingapparatus, including: a packet classifier for classifying and storingthe inputted packet in a multi-queue based on a priority; a queuemanager for including the multi-queue, determining a detour packet amongpackets stored in the multi-queue and marking the packet as the detourpacket; and a packet scheduler for transmitting the packet designated asthe detour packet to the detour path.

In accordance with another aspect of the present invention, there isprovided a packet processing apparatus for processing a packettransmitted from another packet processing apparatus, which is a secondpacket processing apparatus, including: a packet selector for checkingwhether an inputted packet is a normal packet transmitted after beingprocessed in the second packet processing apparatus or a detour packettransmitted without being processed, and directing the packets intocorresponding paths; a queue for storing the detour packet transmittedfrom the packet selector; a packet scheduler for reading the detourpacket stored in the queue and transmitting the detour packet to thepacket processing means in the rear end of the packet processingapparatus; and a packet processor for processing the detour packettransmitted from the packet scheduler and outputting the detour packetas the normal packet.

In accordance with another aspect of the present invention, there isprovided a packet process method for realizing a wire-speed by making aninputted packet detour a packet processor into a detour path andprocessing the inputted packet in a packet processor of another packetprocessing apparatus, which is a second packet processing apparatus,including: a) classifying and storing the inputted packet in amulti-queue based on a priority; b) determining a packet to be detouredamong packets stored in the multi-queue and marking the packet as adetour packet; and c) reading the packet determined as the detour packetout of the multi-queue and transmitting the detour packet to the secondpacket processing apparatus through the detour path.

In accordance with another aspect of the present invention, there isprovided a packet process method for processing a packet transmittedfrom another packet processing apparatus, which is a second packetprocessing apparatus, including: a) checking whether an inputted packetis a normal packet transmitted after being processed in the secondpacket processing apparatus or a detour packet transmitted without beingprocessed, and directing the packets for each path; and b) processingthe directed detour packets and outputting the detour packets as normalpackets.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of the preferredembodiments given in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a diagram showing a packet process of a general line card;

FIG. 2A is a diagram showing a packet process of a line card having adetour packet process function in accordance with an embodiment of thepresent invention;

FIG. 2B is a diagram showing a path of a normal packet in a line cardhaving a detour packet process function in accordance with theembodiment of the present invention;

FIG. 2 c is a diagram showing a path of a detour packet in the line cardhaving a detour packet process function in accordance with theembodiment of the present invention;

FIG. 3 is a diagram showing a format of a normal packet passing throughthe packet processor 225;

FIG. 4 is a diagram showing a format of metadata for marking a detourpacket in accordance with the embodiment of the present invention;

FIG. 5 is a diagram showing a format of a packet requesting packetprocessor using rate information in accordance with the embodiment ofthe present invention;

FIG. 6 is a diagram showing a format of a packet providing packetprocessor using rate information in accordance with the embodiment ofthe present invention;

FIG. 7 is a diagram showing a format of a detour packet formed by apacket scheduler 217;

FIG. 8 is a diagram showing a format of a packet used when the packetscheduler registers the packet processor using rate in a packetprocessor using rate storage in accordance with the embodiment of thepresent invention;

FIG. 9 is a diagram showing a format of a queue lock release packet inaccordance with the embodiment of the present invention;

FIG. 10 is a flowchart describing a packet process method for realizinga wire-speed in accordance with an embodiment of the present invention;and

FIG. 11 is a flowchart describing a packet process method for realizinga wire-speed in accordance with another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Other objects and advantages of the present invention will becomeapparent from the following description of the embodiments withreference to the accompanying drawings. Therefore, those skilled in theart that the present invention is included can embody the technologicalconcept and scope of the invention easily. In addition, if it isconsidered that detailed description on the prior art may blur thepoints of the present invention, the detailed description will not beprovided herein. The preferred embodiments of the present invention willbe described in detail hereinafter with reference to the attacheddrawings.

Although the present invention is applied to a packet communicationsystem such as an Internet Protocol (IP) router, an Ethernet switch anda multi-protocol label switching (MPLS) switch, a process in the IProuter will be described as an example for the sake of convenience inexplanation. However, it is apparent to those skilled in the art thatthe present invention is not limited to the IP router.

Also, the packet communication system, to which the present invention isapplied, includes a plurality of line cards, a switch card, a processorcard for control, and a back plane bus for integrating the cards.

FIG. 1 is a diagram showing a packet process of a general line card. Aprocedure that the packet is inputted through an input port 111 of aline card 110, passes through a series of packet processes and isoutputted to an output port of the other line card through a switch willbe described with reference FIG. 1.

Specifically, the packets, which enter the input port 111, areclassified by a packet classifier 116 and stored in corresponding queues122, 123 and 124. Packets to be assigned to each queue can be classifiedbased on diverse classification standards. One of the most generalmethods for the classification is based on a priority expressed in aheader of each packet.

Diverse methods for designating the priority of the packet are definedin the packet communication system. In case of an Ethernet, the priorityof an Ethernet frame can be designated by using 3 bits with a name ofClass of Service (COS) in the frame header to support quality of service(QoS) in 802.1Q and a P standard. Also, in case of MPLS, the prioritycan be designated by allotting 3 bits with the name of Class of Service(COS). Also, in case of IP packet, the priority of the packet can bedesignated by using 3 bits with the name of Type of Service (TOS) in thepacket header, and in case of DiffServ, the priority of the packet canbe designated by designating a Type of Service (TOS) field of 6 bits.

The packet classifier 116 stores the packet in each of the queues 122,123 and 124 with reference to a bit expressing the priority of thepacket. The packets are filled in an order that the queues 122, 123 and124 enter. The packets stored in the queues 122, 123 and 124 are readbased on a proper order by a packet scheduler 117 and transmitted to apacket processor 125. The packet processor 125 should prepare foraccepting a new packet in order to transmit the packets of the queues122, 123 and 124 to a packet processor 135.

The packet arriving at the packet processor 125 passes through a lookupprocedure of a forwarding table with respect to an IP address and it isdetermined which port of which line card the packet is outputted to.That is, a specific output port 172 is determined among the ports 112,142 and 172. A header for a switching process is added to perform packetswitching in a switch 199. The packet, which the header is added to,passes through a switch output port 113 and is transmitted tocorresponding switch input ports 114, 144 and 174 of the line cards 110,140 and 170.

When it is determined that the packet is outputted to the output port172 of the line card 170, the packet is outputted to an external throughthe output port 172 of the line card after passing through the switchinput port 174 and waiting in an output queue 192 for a while. Thepacket process in the packet processor 125 includes a packet processbased on a definition in Access Control List, a packet metering, aprocess with respect to an MPLS header and diverse processes withrespect to the packet for supporting the QoS as well as the lookup ofthe forwarding table with respect to the packet IP address.

The packet process requiring time in the packet processor 125 is basedon a kind of the packet and comparatively long time is generallyrequired for a complicated process. When the packet process is delayedfor a long time in the packet processor 125, the queues 122, 123 and 124are filled with the packets. The packets entering the queue after thequeues are completely filled with the packets are discarded since thereis no room for storing the packet. Generally, although a poor conditionthat the packets requiring a complicate process are continuouslyinputted is considered when a process capacity of the packet processor125 is designed, there is a possibility that the capacity is not enoughfor the packets.

In the above case, although there is a room for processing the packet inpacket processors 155 and 185 existing in the other line cards 140 and170, it is not helpful. The object of the present invention is to raisethe packet process efficiency by processing the packet, which entersthrough the input port 111, through the packet processors 155 and 185 inthe other line cards 140 and 170 as well as sources in the its own linecard 110, thereby processing the packets entering through each of inputports 111, 141 and 171 at the wire-speed without loss.

FIG. 2A is a diagram showing a packet process of a line card having adetour packet process function in accordance with an embodiment of thepresent invention. The packet process of the normal packet and thedetour packet will be described in detail with reference to FIG. 2A.Herein, the normal packet is processed in the packet processor of theinputted line card and the detour packet is processed after beingtransmitted to the packet processor of the other line card since burdenis too heavy in the packet processor of the line card. A status that thenormal packet and the detour packet are inputted in an input port 211 ofthe line card 210 and outputted to an output port 272 of a line card 270will be described in detail hereinafter.

The path of the normal packet is as follows. The packet entering theinput port 211 passes through a packet classifier 216, is stored in eachof queues 222 and 223, read one by one by a packet scheduler 217 andtransmitted to a packet processor 225. The packet processed in thepacket processor 225 passes through a detour packet scrambler 237, isoutputted to a switch 299 through a switch end output port 213 andtransmitted to a switch end input port 274 of the line card 270 in theswitch 299. Subsequently, the normal packet passes through an outputqueue 292 and is outputted to the output port 272. FIG. 2B is a diagramshowing a path of a normal packet in a line card having a detour packetprocess function in accordance with the embodiment of the presentinvention. A path and a process of the normal packet is the same as thepacket process in the conventional line card described in FIG. 1.

FIG. 3 is a diagram showing a format of a normal packet passing throughthe packet processor 225, and the format of FIG. 3 is formed bydetermining which port of which line card the normal packet is outputtedto while the normal packet passes through a packet process in the packetprocessor 225.

A field of a reference number 310 of FIG. 3 includes a 1-byte targetline card identifier. Herein, the target line card identifier notifieswhich line card the normal packet is transmitted to when the normalpacket passes through the switch 299. A field of the reference number320 includes 1-byte Opcode showing that the packet is a normal packetand a field of a reference number 330 includes 1-byte null data. Thenull data designate data embedded to meet a form with the format of thenormal packet and the detour packet, which will be describedhereinafter, but do not have a specific meaning. Meanwhile, a field of areference number 340 includes 1-byte port number data showing which portof which line card the packet is outputted, and a field of a referencenumber 350 includes an IP packet to be outputted to a final output port.

The target line card identifier 310 is removed while the normal packetformed of the format of FIG. 3 passes through the switch 299, and theOpcode 320 and the port number data 340 are removed while the normalpacket passes through a rear end packet classifier 293. Finally, onlythe IP packet 350 is stored in the output queue 292.

A path of the detour packet is as follows. The packets entering theinput port 211 are stored in queues 222 and 223 through the packetclassifier 216, and it is determined that some of packets staying in thequeue are detour packets. The determined detour packet is inputted to afront end detour path 238 through the packet scheduler 217 and thedetour packet is inputted to the switch 299 through the switch endoutput port 213 after passing through the front end detour packetscrambler 237. The detour packet inputted to the switch 299 istransmitted to a switch end input port 244 of the line card 240 after aswitching process, selected in the rear end packet classifier 263 andinputted to a rear end detour path 264. Subsequently, the detour packetis classified by a packet classifier 246 through a rear end detourpacket scrambler 265, stored in a queue 254, read one by one by a packetscheduler 247 and transmitted to a packet processor 255. The detourpacket processed in the packet processor 255 passes through a front enddetour packet scrambler 267, is outputted to the switch 299 through aswitch end output port 243 and transmitted to the switch end input port274 of the line card 270 in the switch 299. Subsequently, the detourpacket is identified as an output packet by the rear end packetclassifier 293 and outputted to the output port 272 through the outputqueue 292. FIG. 2C is a diagram showing a path of a detour packet in theline card having a detour packet process function in accordance with theembodiment of the present invention.

The process of the detour packet will be described in detailhereinafter. The detour packet enters through the input port 211 and isstored in one of the multi-queues 222 and 223 through a classificationprocedure of the packet in the packet classifier 216. Herein, the detourpacket is selected among packets in the queues 222 and 223 storingpackets of a low priority. In the present embodiment, the packet of thehigh priority is stored in the queues 222 and the packet of the lowpriority is stored in the queues 223. The queue 224 is used to store thepacket entering after being detoured.

When the detour packet is selected, it is preferred to select the packetof the low priority to minimize a negative effect such as packetdelivery delay, which can be generated by the detour process of thepacket. When the packet detour is generated, delay of the packetincreases since the packet should go through one more line card.Therefore, it is preferred to detour the packet of the low prioritysupporting a low-quality service instead of the packet of a highpriority supporting a high-quality service. However, the presentinvention is not limited to the above process.

Meanwhile, there is a well-known method for actively dividing a memoryspace of a regular size and allotting to each queue as one method torealize the multi-queue. The memory space is divided into an areaallotted to the queue and an area not allotted to the queue. Thenon-allotted area of the memory is actively allotted based on necessityof each queue. When the number of packets entering a queue is largerthan the number of the packets getting out of the queue, the queue needsmore space to receive a new packet and a predetermined space of thenon-allotted area are used to make the queue larger. When vacant spaceof the queue increases since the number of the packet filling a queue islarger than the number of the processed packets, remaining vacant spaceis returned to the non-allotted area of an entire sharing memory and thereturned non-allotted area is used again for a vacant space of anotherqueue.

The queue manager 221 continuously checks a possibility that the queuecan be filled with the inputted packets and actively assigns the memoryspace to each queue as described above. A simple method for predictingsaturation of the queue space is to catch a status that the non-assignedarea of the memory decreases less than a certain limit. A morecomplicated method for the prediction is to determine how long it takesto saturate a queue by analyzing the remaining quantity and a decreasingrate of the non-assigned area.

When the saturation of the queue is expected in the above procedure, thequeue manager 221 supports that some packets stored in the queues 223are quickly transmitted to the other line card through the front enddetour path 238 without passing through the packet processor 225.

Also, the queue manager 221 determines a series of P numbers of packetsas packets to be detoured among the packets stored in the queues 223. AP value can be optimized by an experiential method in a procedureoperating a system and can be applied as a variable value. When the P isset up as a small value, a few numbers of packets should be detouredmany times, and when the P value is large, many numbers of packets canbe detoured a few times. A fact that a total number of the detour packetis P is recorded in a detour packet counter. The value of the detourpacket counter decreases by 1 whenever the detour packet is processedone by one. The detour packet counter is recorded by the queue manager221 and means a sharing data area, which can be read in the front enddetour packet processor, i.e., a packet scheduler.

The queue manager 221 marks on the P packets to perform the detourprocess. That is, “detour packet” is marked on the packets. The metadataare used to mark the detour packets.

FIG. 4 is a diagram showing a format of metadata for marking a detourpacket in accordance with the embodiment of the present invention, and afield of a reference number 410 of FIG. 4 includes a 4-byte packet indexformed. The packet index is a pointer pointing a real packet positionand can index to a 2³² address area. A field of a reference number 420includes a detour packet flag showing whether the packet is the detourpacket, e.g., 0:normal and 1:detour, and a field of a reference number430 includes a final detour packet flag showing whether the packet is afinal packet among the P packets. The final detour packet flag is set upas 1 with respect to only a p^(th) detour packet and 0 with respect to a(P−1)^(th) detour packet. A field of a reference number 440 includes a6-bit queue number showing which queue the detour packet comes from anda field of a reference number 450 includes a detour line card identifiershowing a packet processor of which line card is borrowed to process thedetour packet.

Also, the queue manager 221 determines which line card the detour packetis sent to when the packet is processed. It is preferred to process thedetour packet of each line card after transmitting the detour packet toa line card, whose using rate is the lowest, in order to decentralizeload maximally. Information on load of a packet processor of which linecard is the smallest can be acquired by reading data of a packetprocessor using rate storage 280. Registering the using rate of thepacket processor of each line card in the packet processor using ratestorage 280 is registered by the packet scheduler 217 and will bedescribed hereinafter.

The packet processor using rate information that the queue manager 221should know is stored in a sharing memory area in the inside of theswitch card 299. It is preferred to store the packet processor usingrate information in the sharing memory area since a queue manager ineach line card is accessible without a bottleneck effect. The otherarea, which the packet processor using rate information can be storedin, is a memory in the inside of a main processor board. Although thememory of the main processor board is easily accessible, the memory isnot a preferred storing position in consideration of effective using ofresources since there is generally a limit to a link speed. However,storing the packet processor using rate information in the mainprocessor board is not excluded.

When the packet processor using rate information is updated with newestdata, the position of the packet processor used at a smallest quantitycan be acquired. The queue manager 221 can request the packet processorusing rate storage 280 for the newest packet processor using rateinformation. A format of the packet requesting the packet processorusing rate information to the packet processor using rate storage 280will be described with reference to FIG. 5.

FIG. 5 is a diagram showing a format of a packet requesting packetprocessor using rate information in accordance with the embodiment ofthe present invention. A field of a reference number 510 of FIG. 5includes a 1-byte storage identifier notifying that the packet should bedelivered to the packet processor using rate storage 280. Herein, thestored value is 0. A field of a reference number 520 includes 1-byteOpcode showing that the packet requests the packet processor using rateinformation. A field of a reference number 530 includes the 1-byterequest line card identifier showing which line card requests the packetprocessor using rate information, and a field of a reference number 540includes the 1-byte object line card identifier showing which line cardthe packet processor using rate information is for.

When the packet processor using rate storage 280 receives a packetprocessor using rate information request packet having the format ofFIG. 5 from the queue manager 221, the packet processor using ratestorage 280 notifies a packet process rate of the line card bydelivering a packet processor using rate information providing packet,which has a format of FIG. 6, to the queue manager 221 through the rearend detour path 234.

FIG. 6 is a diagram showing a format of a packet providing packetprocessor using rate information in accordance with the embodiment ofthe present invention. A reference number 610 includes the 1-byterequest line card identifier showing the line card to receive the usingrate information, and a reference number 620 includes the 1-byte Opcodeshowing that the packet provides the using rate information of thepacket processor. Also, a reference number 630 includes the 1-byteobject line card identifier showing on which line card the packetprocessor using rate information is, and a reference number 640 includesusing rate data of a 1-byte packet processor expressed as a percentage.

The queue manager 221 grasps recent using rate information byperiodically requesting information on a packet processor using rate ofeach line card to the packet processor using rate storage 280. A nextprocedure will be described on the assumption that it is confirmed thatthere is a room in the packet processor of the line card 240 through theabove procedure.

Subsequently, the packet scheduler 217 reads the packet in the queue,and transmits the packet to the packet processor 225 or the other linecard through the front end detour path 238. It is determined where totransmit the packet with reference to metadata having the format of FIG.4, which is linked to the packet stored in the queue.

The packet scheduler 217 continuously checks a condition of the packetprocessor 225 and confirms whether there is a packet designated as adetour packet in the queue when the packet processor 225 does notprepare for reading the packet. When there is the packet designated asthe detour packet, the packet scheduler 217 reads and transmits thedetour packet to the front end detour packet scrambler 237 through thefront end detour path 238. Herein, the packet scheduler 217 adds aheader to the detour packet as a format of FIG. 7 as described above.When the packet processor 225 prepares for reading the packet, thepacket processor 225 reads the packet in a proper queue based on aschedule and transmits the packet to the packet processor 225.

FIG. 7 is a diagram showing a format of a detour packet formed by thepacket scheduler 217, and the detour packet formed of the format of FIG.7 is inputted to the switch 299 through the front end detour path 238.

A field of a reference number 710 of FIG. 7 includes the 1-byte targetline card identifier. Herein, the target line card identifier notifieswhich line card the detour packet should be transmitted to when thedetour packet passes through the switch 299. A field of a referencenumber 720 includes the 1-byte Opcode showing that the packet is thedetour packet and a field of a reference number 730 includes a detourpacket flag, which is set up to be 1, when the packet is the detourpacket, e.g., 0:normal, 1:detour. A field of a reference number 740includes a final detour packet flag, which is set up to be 1 when thepacket is the final detour packet and a field of a reference number 750includes 6-bit queue number data f showing which queue the detour packetstarts from. A field of a reference number 760 includes a 1-byte homeline card identifier formed showing information of the line card settingup the inputted packet as the detour packet, and a field of a referencenumber 770 includes an IP packet entering the packet processor 255.

While the detour packet formed of the format of FIG. 7 passes throughthe switch 299, the target line card identifier 710 is removed, andwhile the detour packet passes through the rear end packet classifier263, the Opcode 720 is removed. While the detour packet passes throughthe packet scheduler 247, the detour packet flag 730, the final detourpacket flag 740, the queue number 750 and the home line card identifier760 are removed, and only the IP packet 770 is inputted to the packetprocessor 255. The packet processor 255 forms the IP packet 770 of thedetour packet as the format of the normal packet of FIG. 3 and outputsthe IP packet 770.

In the above procedure, the packet scheduler 217 reduces a detour packetcounter one by one whenever the detour packet is processed one by one.The procedure is performed till all packets come out of the queue. Thepackets filling the queue rapidly decrease since the packet stored inthe queue is transmitted through the packet processor 225 and the detourpath 238. Accordingly, a possibility that the queue is saturateddecreases and a room for accepting a new packet can be prepared.

While the packet scheduler 217 processes all detour packets, locks thequeue and accepts the packet in the queue, the packet scheduler 217prevents the packet from going out the queue through the packetprocessor 225 and the detour path 238. Locking the queue is forprotecting an output priority of the packet remaining in the detouredpacket and the queue. That is, locking the queue is for preventing thepacket from going out to an output port in a wrong order.

Also, the packet scheduler 217 measures how much the packet processor225 is busy to process the packets, and stores the result in the packetprocessor using rate storage 280. The using rate information should beupdated as frequently as a condition of the queue can be reflected.Since the present invention suggests a method for using information of apacket process using frequency instead of a detailed method forcalculating a packet process using frequency of a packet processor, adetailed method for determining the packet process using frequency willnot be described herein. The packet processor using rate information ofeach line card is updated in the packet processor using rate storage 280and queue managers of each line card read the packet processor usingrate information of each line card from the packet processor using ratestorage 280. The procedure is described hereinbefore.

FIG. 8 is a diagram showing a format of a packet used when a packetscheduler registers a packet processor using rate in a packet processorusing rate storage in accordance with the embodiment of the presentinvention. A field of a reference number 810 includes the 1-byte storageidentifier showing that the packet should be transmitted to the packetprocessor using rate storage 280 through the switch 299 and a field of areference number 820 includes the 1-byte Opcode showing that the packetrecords the packet processor using rate. Also, a field of a referencenumber 830 includes the 1-byte line card identifier showing a using ratevalue of which line card the field of a reference number 830 designates,and a field of a reference number 840 includes 1-byte percentage dataexpressing how many percentages of packet processors are used.

Subsequently, the detour packet is moved to the front end detour packetscrambler 237 and the front end detour packet scrambler 237 scrambles adetour packet and a normal packet coming from both ways. That is, thefront end detour packet scrambler 237 scrambles the packets byrotationally checking a buffer corresponding to each path. When a speedfor rotationally checking the buffer of both ways is faster than a speedfor filling each buffer with the packets, the packet can be processedwithout delay.

The detour packet passing through the front end detour packet scrambler237 enters the switch 299 through the switch end output port 213. Thedetour packet entering the switch is switched with the line card 240 byinformation recorded in the target line card identifier 710 as shown inFIG. 7. The target line card identifier 710 is removed in the procedureand inputted into the switch end input 244 of the line card 240.

The rear end packet classifier 263 classifies a normal packet and adetour packet coming through the switch end input 244 and dividedlytransmits the normal packet and the detour packet to each path. Whilethe normal packet having the format of FIG. 3 passes through the switch299, the target line card identifier 310 is removed and the Opcode 320showing that the packet is the normal packet is arranged in a front endof the normal packet. While the detour packet having the format of FIG.7 passes through the switch 299, the target line card identifier 710 isremoved and the Opcode 720 showing that the packet is the detour packetis arranged in a front end of the detour packet. The rear end packetclassifier 263 determines whether each packet is the normal packet orthe detour packet with reference to each of the Opcodes 320 and 720.

The normal packet is a packet that the packet is processed in the packetprocessor of the other line card. Therefore, only a process to outputthe normal packet to output port 242 through an output queue 262remains. The detour packet is transmitted to a rear end detour path 264by the rear end packet classifier 263. The detour packet is a packet,which is not processed in its own line card 210, but transmitted to theother line card 240. Therefore, the detour packet should be processed inthe packet processor 255 of the newly arriving line card 240.

The detour packet arrives at the rear end detour packet scrambler 265through the rear end detour path 264. Although it is described as therear end detour packet scrambler 265 functions independently from thepacket classifier 246, it is only for the sake of convenience inexplanation. The rear end detour packet scrambler 265 and the packetclassifier 246 can function and be realized as one module.

The rear end detour packet scrambler 265 scrambles the detour packetarriving through the rear end detour path 264 and the packet comingthrough an input port 241 of the the line card 240 as one path. Thescrambled detour packet and normal packet are classified by the packetclassifier 246 based on the priority and stored in the queue. A queue252 stores the packet of a high priority and a queue 253 stores thepacket of a low priority. Although the queues are divided into two basedon the priority in FIG. 2, there can be more queues divided based on thepriority.

The queue 254 stores the detour packet. Therefore, the detour packetenters the rear end detour packet scrambler 265 through the rear enddetour path 264 and stored in the queue 254 through the packetclassifier 246. A procedure that the packet scheduler 247 transmits thepacket of the queue to the packet processor 255 or the front end detourpath 268 by reading the packet one by one based on the scheduling is thesame as the above description. Herein, the detour packet detoured fromthe other line card cannot be transmitted to the other line card throughthe front end detour path 268. Therefore, packets stored in the queue254 are transmitted to the packet processor 255 by the packet scheduler247.

A packet process such as an address lookup is performed on the detourpacket transmitted to the packet processor 255 and the detour packet isgenerated as the normal packet of the format of FIG. 3. The packetpassing through the packet processor 255 enters the switch 299 throughthe front end detour packet scrambler 267 and the switch end output port243. When the packet switched in the switch 299 enters the rear endpacket classifier 293 of the line card 270 through the switch end inputport 274 and outputted to the output port 272 after staying in theoutput queue 292 for a while, all procedures of the detour packetprocess are finished.

In a procedure that the detour packet is transmitted from the packetscheduler 247 to the packet processor 255, a final detour packet checker266 checks whether the detour packet, which is processed in the presenttime, is the final detour packet or not. That is, while the detourpacket formed of the format of FIG. 7 passes through the switch 299, thetarget line card identifier 710 is removed. While the detour packetpasses through the rear end packet classifier 263, the Opcode 720 isremoved. Herein, the final detour packet checker 266 checks whether thedetour packet is the final detour packet or not through the detourpacket flag 730 and the final detour packet flag 740, and the detourpacket flag 730 and the final detour packet flag 740 are removed.

Although it is described as the final detour packet checker 266functions dependently from the packet scheduler 247, the final detourpacket checker 265 and the packet scheduler 246 can function and berealized as one module.

Meanwhile, as described above, the packet scheduler 217 of the line card210 transmits the final detour packet in a series of detour packets,locks the queue and accepts the packet in the queue. However, the packetscheduler 217 does not transmit the packet. The final detour packetchecker 266 releases the locked queues 223.

The final detour packet checker 266 checks the home line card identifier760 which line card the detour packet comes from and checks the queuenumber 750 which queue the detour packet comes from. Subsequently, thefinal detour packet checker 266 removes the home line card identifier760 and the queue number 750. The final detour packet checker 266transmits the same queue lock release packet as shown in FIG. 9 to thepacket scheduler 217 of the line card 210 after the procedure.

FIG. 9 is a diagram showing a format of a queue lock release packet inaccordance with the embodiment of the present invention. A field of areference number 910 of FIG. 9 includes the 1-byte line card identifierdesignating the line card, on which the locked queue exists, and a fieldof a reference number 920 includes the Opcode showing that the packet isthe queue lock release packet. A field of a reference number 930includes a 1-byte or 6-bit queue number designating the locked queue ofthe line card.

The queue lock release packet having the format of FIG. 9 enters aswitch end input port 214 through the front end detour path 268, thefront end detour packet scrambler 267, the switch end output port 243and the switch 299 and arrives at the packet scheduler 217 through arear end packet classifier 233, the rear end detour path 234, a rear enddetour packet scrambler 235, the packet classifier 216 and the queue224. The queue lock release packet releases the locked queues 223 afterthe packet scheduler 217 transmits the detour packet and. Subsequently,the queues 223 attend the scheduling object of the packet scheduler 217and starts transmitting the packet to the packet processor 223.

FIG. 10 is a flowchart describing a packet process method for realizinga wire-speed in accordance with an embodiment of the present invention.

As shown in FIG. 10, at step S1001, the packet classifier 216 stores aninput packet in multi-queues 222 and 223 based on a priority, and atstep S1002, the queue manager 221 determines saturation possibilities ofthe queues 222 and 223 by the inputted packets.

When the queues 222 and 223 are expected to be saturated, the queuemanager 221 determines a series of P packets to be detoured among thepackets stored in the queues 223 at step S1003, and records the factthat there are P detour packets in the detour packet counter at stepS1004.

At step S1005, the queue manager 221 generates the metadata as theformat of FIG. 4 with respect to the determined P detour packets.

At step S1006, the packet scheduler 217 continuously checks thecondition of the packet processor 225 and determines whether the packetprocessor 225 prepares for reading the packet.

At step S1011, when the packet processor 225 prepares for reading thepacket, the packet scheduler 217 reads the packets stored in the queues222 and 223 based on a proper order and transmits the packets to thepacket processor 225. The packet processor 225 forms the received packetas the format of FIG. 3 and outputs the packet to the destination linecard.

At step S1007, when the packet processor 225 does not prepare forreading the packet, the packet scheduler 217 reads the detour packetstored in the queue 223 one by one with reference to the metadata havingthe format of FIG. 4 and transmits the detour packet to the other linecard through the front end detour path 238 by adding a header as theformat of FIG. 7.

At step S1008, the packet scheduler 247 reduces the detour packetcounter one by one whenever the detour packets are processed one by one.At steps S1009 and S1010, when all detour packets are transmitted to theother line card through the front end detour path 238, the packetscheduler 247 locks the queue 223. Locking the queue 223 is forprotecting an output order of the packets which remain in the detouredpacket and the queues 223. That is, the queue 223 is locked to preventthe packets from going out to the output port based on a wrong order.

FIG. 11 is a flowchart describing a packet process method for realizinga wire-speed in accordance with another embodiment of the presentinvention. A case that the detour packet, which is transmitted throughthe detour path without being processed in the line card 210 and 270,and the normal packet, which is transmitted after normally processed inthe line cards 210 and 270, is inputted the line card 240 will bedescribed as an example. Herein, it is assumed that a destination outputport of the detour packet is the output port 272 and the destinationoutput port of the normal packet is the output port 242.

While the normal packet formed of the format of FIG. 3 in the packetprocessors 225 and 285 of the line cards 210 and 270 passes through theswitch 299, the target line card identifier 310 is removed and thenormal packet is inputted. While the detour packet, which is notprocessed in the line cards 210 and 270 but transmitted through thedetour path after being formed of the format of FIG. 5, passes throughthe switch 299, the target line card identifier 540 is removed and thedetour packet is inputted to the rear end packet classifier 263.

As shown in FIG. 11, at step S1101, the rear end packet classifier 263determines whether each packet is the normal packet or the detour packetwith reference to the Opcodes 320 and 720.

At step S1110, while the normal packet passes through the rear endpacket classifier 263, the normal packet is transmitted to the outputqueue 292 after the Opcode 320 and the port number data 340 are removed,and only the IP packet 350 is finally outputted to the output port 242.

Meanwhile, at step S1102, while the detour packet passes through therear end packet classifier 263, the Opcode 720 is removed. At stepS1103, the detour packet, in which the Opcode 720 is removed, enters therear end detour packet scrambler 265 through the rear end detour path264 and is stored in the queue 254 through the packet classifier 246.Although it is described as the rear end detour packet scrambler 265functions independently from the packet classifier 246 for the sake ofconvenience in explanation, the rear end detour packet scrambler 265 andthe packet classifier 246 can function and be realized as one functionalmodule.

The packet scheduler 247 transmits the detour packet stored in the queue254 to the packet processor 255 after reading the detour packet one byone based on the scheduling. At step S1104, the final detour packetchecker 266 checks the detour packet flag 730 and the final detourpacket flag 740 whether the detour packet is the final detour packet,and removes the detour packet flag 730 and the final detour packet flag740 at steps S1105 and S1106. Although it is described as the finaldetour packet checker 266 functions independently from the packetscheduler 247 for the sake of convenience in explanation, a function ofthe final detour packet checker 265 is a part of functions of the packetclassifier 246.

In case of the final detour packet, the final detour packet checker 266checks the home line card identifier 760 of the detour packet to knowwhich line card the detour packet comes from and the queue number 750 toknow which queue the detour packet comes from, and removes the home linecard identifier 760 and the queue number 750 at step S1107.

At step S1108, the final detour packet checker 266 generates andtransmits the same queue lock release packet as FIG. 9 to the packetscheduler of the line card, which corresponds to the home line cardidentifier 760.

At step S1109, the packet processor 255 generates the IP packet of thedetour packet as the format of the same normal packet as FIG. 3 andtransmits the packet to the line card.

The present invention can improve a performance of each packetprocessing apparatus by sharing and using packet process resources ofthe other packet processing apparatus existing in the inside of acommunication system instead of selecting a high-performance processoras a method for raising a process rate of the packet in the packetprocessing apparatus.

Therefore, the substantial packet process performance can be expressedas an addition of packet process resources, of the packet processingapparatus, and packet process resources, which are not used in allpacket processing apparatuses mounted in an inside of the communicationsystem.

That is, the present invention is economical since the present inventiondoes not generate an additional cost by borrowing and applying thepacket process resources, which are not used in each packet processingapparatus.

As described in detail, the present invention can be embodied as aprogram and stored in a computer-readable recording medium, such asCD-ROM, RAM, ROM, a floppy disk, a hard disk and a magneto-optical disk.Since the process can be easily implemented by those skilled in the art,further description will not be provided herein.

The present application contains subject matter related to Korean patentapplication Nos. 2004-0103170 and 2005-0101668, filed with the KoreanIntellectual Property Office on Dec. 8, 2004, and Oct. 27, 2005,respectively, the entire contents of which are incorporated herein byreference.

While the present invention has been described with respect to certainpreferred embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the scope of the invention as defined in the following claims.

1. A packet processing apparatus by making an inputted packet detour apacket processor into a detour path and processing the inputted packetin a packet processing means of another packet processing apparatus,which is a second packet processing apparatus, comprising: a packetclassifying means for classifying and storing the inputted packet in amulti-queue based on a priority; a queue managing means for includingthe multi-queue, determining a detour packet among packets stored in themulti-queue and marking the packet as the detour packet; and a packetscheduling means for transmitting the packet designated as the detourpacket to the detour path.
 2. The apparatus as recited in claim 1,wherein the queue managing means marks the detour packet by usingmetadata, wherein the metadata include: a field for providing positioninformation of a packet; a field for providing information on whether apacket is a final detour packet; a field for providing information onwhich queue the packet comes from; and a field for providing informationon which packet processing apparatus the packet is transmitted to. 3.The apparatus as recited in claim 2, wherein the packet scheduling meanstransmits the packet designated as the detour packet to the detour pathwith reference to the metadata.
 4. The apparatus as recited in claim 1,wherein the packet scheduling means adds a header to the packetdesignated as the detour packet, and the header includes: a field forproviding information on which packet processing apparatus the packet istransmitted to; a field for providing information on whether the packetis the detour packet; a field for providing information on whether thepacket is the final detour packet; a field for providing information onwhich queue the packet comes from; and a field for providing informationon the packet processing apparatus that sets up the packet as the detourpacket.
 5. The apparatus as recited in claim 1, wherein the queuemanaging means determines a packet processing apparatus to receive thedetour packet based on packet process rate information of the secondpacket processing apparatus which is stored in an external packetprocess rate storing means.
 6. The apparatus as recited in claim 5,wherein the queue managing means acquires the packet process rateinformation of the second packet processing apparatus by transmitting apacket process rate information request packet to the packet processrate storing means.
 7. The apparatus as recited in claim 6, wherein thepacket process rate information request packet includes: a field forproviding information showing that the packet should be transmitted tothe packet process rate storing means; a field for providing informationshowing that the packet requests the packet process rate information; afield for providing information of the packet processing apparatusrequesting the packet process rate information; and a field forproviding information on which packet processing apparatus the packetprocess rate information request is for.
 8. The apparatus as recited inclaim 6, wherein the packet process rate storing means transmits apacket process rate information providing packet in responds to thepacket process rate information request packet transmitted from thequeue managing means.
 9. The apparatus as recited in claim 8, whereinthe packet process rate information providing packet includes: a fieldfor providing information of the packet processing apparatus to receivethe packet process rate information; a field for showing that the packetprovides the packet process rate information; a field for providinginformation on which packet processing apparatus the packet process rateinformation is for; and a field for providing the packet process rateinformation of the requested packet processing apparatus.
 10. Theapparatus as recited in claim 1, wherein the packet scheduling meansregisters the packet process rate information of the packet processingapparatus by transmitting a packet process rate registration packet theexternal packet process rate storing means.
 11. The apparatus as recitedin claim 10, wherein the packet process rate registration packetincludes: a field for providing information showing that the packetshould be transmitted to the packet process rate storing means; a fieldfor providing information showing that the packet registers the packetprocess rate; a field for providing information on which packetprocessing apparatus the packet process rate belongs to; and a field forproviding the packet process rate information of the packet processingapparatus.
 12. The apparatus as recited in claim 1, wherein the queuemanaging means records the number of the packets to be detoured in adetour packet counter.
 13. The apparatus as recited in claim 12, whereinthe packet scheduling means reduces a counting number of detour packetcounter one by one whenever the detour packet is processed one by one,and locks the queue after all detour packets are processed.
 14. A packetprocessing apparatus for processing a packet transmitted from anotherpacket processing apparatus, which is a second packet processingapparatus, comprising: a packet selecting means for checking whether aninputted packet is a normal packet transmitted after being processed inthe second packet processing apparatus or a detour packet transmittedwithout being processed, and directing the packets into correspondingpaths; a queue for storing the detour packet transmitted from the packetselecting means; a packet scheduling means for reading the detour packetstored in the queue and transmitting the detour packet to the packetprocessing means in the rear end of the packet processing apparatus; anda packet processing means for processing the detour packet transmittedfrom the packet scheduling means and outputting the detour packet as thenormal packet.
 15. The apparatus as recited in claim 14, wherein thepacket selecting means determines whether the inputted packet is thenormal packet or the detour packet based on an Opcode.
 16. The apparatusas recited in claim 14, wherein the detour packet stored in the queueincludes: a field for providing information on whether the packet is adetour packet; a field for providing information on whether the packetis a final detour packet; a field for providing information on whichqueue the packet comes from; and a field for providing information ofthe packet processing apparatus which sets up the packet as the detourpacket.
 17. The apparatus as recited in claim 16, wherein the packetscheduling means generates a queue lock release packet based on fieldinformation of the detour packet and transmits the queue lock releasepacket to the packet processing apparatus which transmits the detourpacket.
 18. The apparatus as recited in claim 17, wherein the queue lockrelease packet includes: a field for providing information of the packetprocessing apparatus that a locked queue exists; a field for providinginformation showing that the packet is the queue lock release packet;and a field for providing information of the locked queue.
 19. Theapparatus as recited in claim 16, wherein the packet scheduling meansremoves the field of the detour packet and transmits only a pure IPpacket to the packet processing means.
 20. The apparatus as recited inclaim 14, wherein the normal packet of the packet selecting meansincludes: a field for providing information showing that the packet is anormal packet; a field for providing port number information that thepacket us outputted; and a field which includes an IP packet to befinally outputted, wherein the packet selecting means transmits the IPpacket of the normal packet to a queue connected to a port of the portnumber.
 21. A packet processing method by making an inputted packetdetour a packet processor into a detour path and processing the inputtedpacket in a packet processing means of another packet processingapparatus, which is a second packet processing apparatus, comprising: a)classifying and storing the inputted packet in a multi-queue based on apriority; b) determining a packet to be detoured among packets stored inthe multi-queue and marking the packet as a detour packet; and c)reading the packet determined as the detour packet out of themulti-queue and transmitting the detour packet to the second packetprocessing apparatus through the detour path.
 22. The method as recitedin claim 21, wherein metadata are generated to mark the detour packet inthe step b), the metadata including: a field for providing positioninformation of the packet; a field for providing information on whetherthe packet is a final detour packet; a field for providing informationon which queue the packet comes from; and a field for providinginformation on which packet processing apparatus the packet istransmitted to.
 23. The method as recited in claim 22, wherein thedetour packet is read out of the multi-queue based on the metadata andtransmitted to the second packet processing apparatus through the detourpath in the step c).
 24. The method as recited in claim 21, wherein aheader is added to the detour packet and the detour packet istransmitted to the second packet processing apparatus through the detourpath in the step c), the header including: a field for providinginformation on which packet processing apparatus the packet istransmitted to; a field for providing information on whether the packetis a detour packet; a field for providing information on whether thepacket is a final detour packet; a field for providing information onwhich queue the packet comes from; and a field for providing informationon the packet processing apparatus which sets up the packet as thedetour packet.
 25. The method as recited in claim 21, wherein the stepb) includes: b1) transmitting a packet process rate information requestpacket to an external packet process rate storing means in order toacquire packet process rate information of the second packet processingapparatus; and b2) determining a packet processing apparatus forreceiving packet process rate information providing packet from thepacket process rate storing means and transmitting the packet determinedas the detour packet
 26. The method as recited in claim 25, wherein thepacket process rate information request packet includes: a field forproviding information showing that the packet should be transmitted tothe packet process rate storing means; a field for providing informationshowing that the packet requests the packet process rate information; afield for providing information of the packet processing apparatusrequesting the packet process rate information is for; and a field forproviding information on which packet processing apparatus the packetprocess rate information request is for.
 27. The method as recited inclaim 25, wherein the packet process rate information providing packetincludes: a field for providing information of the packet processingapparatus to receive the packet process rate information; a field forproviding information showing that the packet provides the packetprocess rate information; a field for providing information on whichpacket processing apparatus the packet process rate information is for;and a field for providing packet process rate information of a requestedpacket processing apparatus.
 28. The method as recited in claim 21,further comprising: d) registering the packet process rate informationof the packet processing apparatus by transmitting a packet process rateregistration packet to an external packet process rate storing means.29. The method as recited in claim 28, wherein the packet process rateregistration packet includes: a field for providing information showingthat the packet should be transmitted to the packet process rate storingmeans; a field for providing information showing that the packetregisters a packet process rate; a field for providing information onwhich packet processing apparatus the packet process rate is for; and afield for providing information the packet process rate of the packetprocessing apparatus.
 30. The method as recited in claim 21, furthercomprising: e) recording the number of packets to be detoured in thedetour packet counter; and f) reducing a counting number of the detourpacket counter one by one whenever the detour packet is processed one byone.
 31. The method as recited in claim 30, further comprising: g)processing all packets to be detoured and locking the queue.
 32. Apacket processing method for processing a packet transmitted fromanother packet processing apparatus, which is a second packet processingapparatus, comprising: a) checking whether an inputted packet is anormal packet transmitted after being processed in the second packetprocessing apparatus or a detour packet transmitted without beingprocessed, and dividing the packets into each path; and b) processingthe divided detour packets and outputting the detour packet as thenormal packet.
 33. The method as recited in claim 32, wherein it isdetermined in the step a) whether the packet is a normal packet or adetour packet based on a Opcode of the packet transmitted from thesecond packet processing apparatus.
 34. The method as recited in claim32, wherein the detour packet includes: a field for providinginformation on whether the packet is a detour packet; a field forproviding information on whether the packet is a final detour packet; afield for providing information on which queue the packet comes from;and a field for providing information on the packet processing apparatusthat sets up the packet as a detour packet.
 35. The method as recited inclaim 34, further comprising: c) generating a queue lock release packetbased on the field information of the detour packet and transmitting thequeue lock release packet to the packet processing apparatus whichtransmits the detour packet.
 36. The method as recited in claim 35,wherein the queue lock release packet includes: a field for providinginformation of the packet processing apparatus having a locked queue; afield for providing information showing that the packet is a queue lockrelease packet; and a field for providing information of the lockedqueue.
 37. The apparatus as recited in claim 32, wherein the normalpacket processed in and transmitted from the second packet processingapparatus includes: a field for providing information showing that thepacket is a normal packet; a field for providing port number informationthat the packet is outputted; and a field including an IP packet to befinally outputted.